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Digital Logic Design Lab (訾頛航身閮撖衣), Spring 2010


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Note Date Content
 NEW 2010/06/21 摮銝銋急蝮曉歇銝喉亙蝮暹憿嚗隢6/27銝12暺銋撖思縑乓 [link]
 NEW 2010/06/21 摮銝脫急蝮曉歇銝喉亙蝮暹憿嚗隢6/25銝7暺銋撖思縑靘207-2 [link]
  2010/06/14 Slides for Lab 14 are uploaded. [link]
  2010/05/28 Slides for Lab 13 are uploaded. [link]
  2010/05/21 Slides for Lab 12 are uploaded. [link]
  2010/05/14 Slides for Lab 11 are uploaded. [link]
  2010/05/07 Slides for Lab 10 are uploaded. [link]
  2010/04/30 Slides for Lab 9 are uploaded. [link]
  2010/04/23 摮銝銋隞憭拙祕隤脰亙歇蝬摰X撖阡摮賂撠曹靘銝隤脖
  2010/04/16 Slides for Lab 8 are uploaded. [link]
  2010/04/10 摮銝銋 Report 6 閮勗摮貊勗批捆訾撮銋嚗撠文嗆鈭摮貊撘批捆銝璅∩璅(蝛箇賡賭璅)嚗隢摮訾摰閬閮剜鈭閫嚗銝臭誑靘撣恬航玨祈剝賣嚗血瘝摮詨唳航芸楛憭梧銝銝剜思璈閰虫航質銝
  2010/04/09 Slides for Lab 7 are uploaded. [link]
  2010/04/04 撖阡敹敺蝜喃漱瘜銝閬質”撌脣砍潸玨蝔蝬脤Grading摮貉交雿璆剔像鈭斗蝮曆憿嚗隢蝡唾撣怨舐窗 [link]
  2010/04/02 Slides for Lab 6 are uploaded. [link]
  2010/03/26 Slides for Lab 5 are uploaded. [link]
  2010/03/19 Slides for Lab 4 are uploaded. [link]
  2010/03/12 Slides for Lab 3 are uploaded. [link]
  2010/03/05 Slides for Lab 1 and Lab 2 are uploaded. [link]
  2010/03/01 New slides "箇撖阡閮剖隤霅 - 隞嗉其蝝" has been uploaded.

Digital Design with CPLD Applications and VHDL, 2/e, by Robert Dueck, Thomson
     


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Yuan-Hao Chang
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