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Journal of Information Science and Engineering, Vol. 32 No. 1, pp. 1-25 (January 2016)

Memory Power Optimization on Different Memory Address Mapping Schemas*

1IOT Perception Mine Research Center
China University of Mining and Technology
2The National and Local Joint Engineering Laboratory
Internet Application Technology on Mine
E-mail: {zzw1988; yjhu}
Xuzhou, 22100 P.R. China
3Department of Computer Science and Technology
University of Science and Technology of China
E-mail: {llxx; xhzhou}
Hefei, 230027 P.R. China

Memory accounts for a large and increasing fraction of the energy consumed by computers. To save energy, memory manufacturers design memory devices in different power/work modes. Hardware and software power controls have been proposed to take full advantage of these different modes. In this paper, we analyze the effects of different memory address mapping schemas on power mode control. Note that a memory address mapping schema translates a given physical address to a specific memory cell in DRAM system. We find that most of existing power mode controls are sensitive to memory address mapping schemas that can be categorized as high-bit multi-access cross memory (HMCM) and low-bit multi-access cross memory (LMCM). For the former schema, we propose a rank-sensitive buddy system (RS-Buddy) to cluster pages together to prolong memory modules°¶ time in low power mode. For the latter schema, we introduce a comprehensive solution named MSPA. It adopts a memory address segmentation module to split memory into many regions, configured as different mapping schemas. With the help of an OS power-aware memory allocator, MSPA dynamically allocates one application°¶s memory from its preferred region to balance power and performance. Extensive experiments on practical platform for HMCM show that RS-Buddy can adapt to finer-grained schemas and effectively optimize memory power efficiency. Furthermore, our simulation results of LMCM demonstrate that MSPA can further improve the power efficiency by 3% to 17% when combined with previous arts.

Keywords: mapping schema, memory allocator, power, operating system, buddy system

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Received October 1, 2014; revised January 24, 2015; accepted March 3, 2015.
Communicated by Cho-Li Wang.
* This work is an extension of [25] and includes more than 30% new content: (a) A fine-grained HMCM schema classification, including the linear and interleaved mapping schema; (b) Experiments on real Samsung platform, proving power optimization on LMCM is more meaningful; (c) Three algorithms 2, 3 and 4 are introduced; (d) The impacts of DMA memory accesses on boundary registers configuration are discussed; (e) Several experiments are separately introduced to prove our solution effect in linear and interleaved mapping schema; (f) More experiments on MSPA including the application°¶s bandwidth and rank idle time are discussed in detail; (g) New sensitivity studies chapter is discussed, involving up to three aspects: the region boundary configuration, core counts and the number of ranks.