中央研究院 資訊科學研究所

Reliable and efficient power delivery is critical to
high-performance, power-constrained computing systems. As designers
seek to contain the power consumption of microprocessors through
reductions in supply voltage and power-saving techniques such as
clock-gating, these systems suffer increasingly large power supply
fluctuations due to the finite impedance of the power supply network.
These supply fluctuations, referred to as voltage emergencies, must
be managed to guarantee correctness. Traditional approaches to
address this problem incur high-cost or compromise power/performance
efficiency. Our research seeks ways to handle these alarm conditions
through a combined hardware/software approach, motivated by root
cause analysis of voltage emergencies revealing that many of these
events are heavily linked to both program control flow and
microarchitectural events (cache misses and pipeline flushes). This
talk will discuss three aspects of the project: (1) a fail-safe
mechanism that provides hardware guaranteed correctness; (2) a
voltage emergency predictor that leverages control flow and
microarchitectural event information to predict voltage emergencies
up to 16 cycles in advance; and (3) a proof-of-concept dynamic
compiler implementation that demonstrates that dynamic code
transformations can be used to eliminate voltage emergencies from
the instruction stream with minimal impact on performance.

 

 

Bio:
David Brooks joined Harvard University in September of 2002 and is
a Gordon McKay Professor of Computer Science. Dr. Brooks received
his B.S. (1997) degree from the University of Southern California
and his M.A. (1999) and Ph.D (2001) degrees from Princeton
University, all in Electrical Engineering. Prior to joining Harvard
University, Dr. Brooks was a Research Staff Member at the IBM T.J.
Watson Research Center. His research interests include architecture
and runtime software approaches to address power, reliability, and
variability issues for embedded and high-performance computer
systems.