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Digital Logic Design Lab (訾頛航身閮撖衣), Fall 2010


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Lecturing Information
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Note Date Content
 NEW 2011.01.15 The final score has been announced. Please contact me by Wednesday morning if you have any question. [Go to Grading]
  2010.11.30 The slides of "05 - DE0 with QuartusII" have been uploaded. [Go to slides]
  2010.11.23 The slides of "03 - Logic Gates and 04 - Combinational Logic" have been uploaded. [Go to slides]
  2010.11.09 The slides of "02 - Introduction to Digital IC" have been uploaded. [Go to slides]
  2010.10.19 There will be no class on Oct. 26. The next class on November 2 is in Room 105 (蝬蝘105).
  2010.10.15 The slides of "01 - Introduction to Components and Equipments" have been uploaded. [Go to slides]

Digital Design with CPLD Applications and VHDL, 2/e, by Robert Dueck, Thomson
     


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Yuan-Hao Chang
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