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Digital Logic Design Lab (
訾頛航身閮撖衣
), Spring 2011
Announcement
Lecturing Information
Slides
Grading
Slides (
隤脩敶梁
)
Lecturing Slides (銝隤脫敶梁)
Introduction to Components and Equipments
Introduction to Digital IC
Logic Gates
Combinational Logic
DE0 with QuartusII
VHDL Introduction
Combinational Logic Functions
MUX/DMUX and Full Adder
Sequential Logic - Latch
Sequential Logic - Flip Flop
Shift Registers
State Machine
Memory
Microprocessors
Terasic DE0 FPGA Development Board (FPGA Chip: EP3C16F484C6)
Quars II download:
http://www.altera.com/download
DE0 Installation (DE0 Getting Started)
DE0 User Manual
DE0 Control Panel
DE0 Schematic
USB Blaster Driver for Windows 7
VHDL References
VHDL Cookbook
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Yuan-Hao Chang
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