Institute of Information Science, Academia Sinica



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CITI--Designing Embedded Multiprocessor Networks-on-Chip with Users in Mind

  • LecturerChen-Ling (Jenny) Chou (System Level Design Group, Electrical and Computer Engineering Department, Carnegie Mellon University)
    Host: Dr. Ming-Syan Chen
  • Time2010-01-07 (Thu.) 10:30 – 12:00
  • LocationAuditorium 106 at new IIS Building
Abstract: Over recent years, embedded systems have gained an enormous amount of processing power and functionality. However, it can be seen that the success of embedded systems (or products) happens through users/customers selection and the products which fit user demands the best become prevalent. In this talk, we are going to see how to design such systems with user in mind. First, I will present a user-centric design methodology targeting heterogeneous embedded systems-on-chip where communication happens via the network-on-chip (NoC) approach. More precisely, in this new design methodology, we consider explicitly the information about the user experience and apply machine learning techniques to develop a design flow which aims at minimizing the workload variance; this allows the system to better adapt to different types of user needs and workload variations. Second, we will describe some difficulties for user-centric design, the related machine learning techniques for solving them, and challenges for extending this design philosophy to the general class of embedded systems. Bio: Chen-Ling (Jenny) Chou received the B.S. in Electrical and Control Engineering and M.S. degrees in Electronics Engineering at National Chiao Tung University, Taiwan, in 2002 and 2004, respectively. She is currently pursuing the Ph.D. degree in Electrical and Computer Engineering at Carnegie Mellon University, Pittsburgh, Pennsylvania. Her research interests include communication-centric design methodologies for large-scale system-on-chip, user-centric design methodology for heterogeneous embedded systems, algorithms and architectures for multiprocessor systems, and any fault tolerant techniques for system optimization. She was an intern in Strategic CAD Lab at Intel Corporation during the fall of 2008, working on problems in communication fabric optimization for multiprocessor system-on-chips.