Institute of Information Science, Academia Sinica



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Low Power/Low Voltage Computing

  • LecturerDr. Shih-Lien Lu (Intel)
    Host: Director Pen-Chung Yew
  • Time2011-01-27 (Thu.) 14:00 – 15:00
  • LocationAuditorium 101 at new IIS Building



Power is one of the key factor in computing system design. One 
of the most effective techniques to reduce a processor’s power 
consumption is to reduce supply voltage. However, reducing 
voltage in the context of dynamic and static variations can 
cause circuits to fail. As a result, voltage scaling is limited
 by a minimum voltage below which circuits may not operate 
reliably. In this talk we will discuss opportunities for 
resiliency to improve energy efficiency of computing in scaled 
CMOS technologies. 




Shih-Lien Lu received his B.S. in EECS from UC Berkeley, and 
M.S. and Ph.D. in CSE from UCLA. He had worked as a design manager 
on the MOSIS project at USC/ISI and served on the faculty at 
Oregon State University’s ECE department. Currently he is a 
Principal Scientist and leads a research group in Intel Labs 
on micro architecture.