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Journal of Inforamtion Science and Engineering, Vol.14 No.2, pp.499-514 (June 1998)
Performance of Shared Caches on
Multithreaded Architectures

Yunn-Yen Chen, Jih-Kwon Peir* and Chung-Ta King#
ATC, Computer and Communication Research Lab.
Industrial Technology Research Institute
Hsinchu, Taiwan 310, R.O.C.
* Department of Computer and Information Science
University of Florida Gainesville, FL, 32611
# Department of Computer Science
National Tsing Hua University
Hsinchu, Taiwan 300, R.O.C.

A multithreaded computer maintains multiple program counters and register files to support concurrent or overlapping execution of multiple threads of context, and to provide fast context switching for tolerance of memory latency. In this paper, we apply trace-driven simulation to study the performance impact of a multithreaded architecture on the storage hierarchy. In particular, we examined the effects of different multithread scheduling techniques on cache performance. Using several program traces representing a typical server/workstation workload mix, we find that cache performance can be improved over that of the traditional round-robin scheduling method when the thread with the MRU hit is given a higher priority. With a direct-mapped cache, the absolute hit ratio can be improved by more than 7%. We also study the performance effects of the multithreading degree, i.e., the number of threads coexisting in the processor at the same time, on cache memory. The results show that both cache size and set associativity need to increase according to the multithreading degree in order to maintain comparable cache performance.

Keywords: computer architecture, multithreaded execution, cache system, performance evaluation, scheduling

Received April 28, 1995; revised march 10, 1998.
Communicated by Chuan-Lin Wu.