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Journal of Inforamtion Science and Engineering, Vol.14 No.3, pp.523-545 (September 1998)
A Unified Approach to Object-Oriented VHDL1

Martin Radetizki, Wolfram Putzke-Roming and Wolfgang Nebel
OFFIS Research Institute Escherweg 2
26121 Oldenburg, Germany

Abstraction and reuse are keys to dealing with the increasing complexity of electronic systems. We apply object-oriented modeling to achieve more reuse and higher abstraction in hardware design. This requires an object-oriented hardware description language, preferably an extension of VHDL. Several variants of such OO-VHDL are currently being debated. We present our unified approach, Objective VHDL, which adds object-oriented features to the VHDL design entity as well as to the type system to provide maximum modeling power.

Keywords: hardware, design, modeling, system level, reuse, object-oriented, VHDL.

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Received October 31, 1997; revised March 18, 1998.
Communicated by Jin-Yang Jou.
1 This work was funded as part of the OMI-ESPRIT project REQUEST under contract 20616. This article is based on a paper [1] published and copyrighted by the 4th Asia-Pacific Conference on Hardware Description Languages (APCHDL '97).