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Journal of Information Science and Engineering, Vol. 23 No. 1, pp. 71-90 (January 2007)

A Tableless Approach for High-Level Power Modeling Using Neural Networks*

Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu and Jing-Yang Jou
Department of Electronics Engineering
National Chiao Tung University
Hsinchu, 300 Taiwan
E-mail: {hsucy; jyjou}
+Department of Electrical Engineering
National Central University
Taoyuan, 320 Taiwan
E-mail: {wthsieh; jimmy}

For complex digital circuits, building their power models is a popular approach to estimate their power consumption without detailed circuit information. In the literature, most of power models have to increase their complexity in order to meet the accuracy requirement. In this paper, we propose a tableless power model for complex circuits that uses neural networks to learn the relationship between power dissipation and input/ output signal statistics. The complexity of our neural power model has almost no relationship with circuit size and number of inputs and outputs such that this power model can be kept very small even for complex circuits. Using such a simple structure, the neural power models can still have high accuracy because they can automatically consider the non-linear characteristic of power distributions and the effects of both statedependent leakage power and transition-dependent switching power. The experimental results have shown the accuracy and efficiency of our approach on benchmark circuits and one practical design for different test sequences with wide range of input distributions.

Keywords: power macromodel, power estimation, neural network, low power design, RTL

Full Text () Retrieve PDF document (200701_04.pdf)

Received November 8, 2004; revised January 19, 2005; accepted March 23, 2005.
Communicated by Chung-Yu Wu.
*This work was supported in part by the National Science Council of Taiwan, R.O.C., under contract No. NSC 93-2215-E-008-031.