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Journal of Information Science and Engineering, Vol. 23 No. 3, pp. 911-923 (May 2007)

Improved Modulo (2n + 1) Multiplier for IDEA*

Yi-Jung Chen1, Dyi-Rong Duh2 and Yunghsiang Sam Han3
1Department of Computer Science and Information Engineering
National Taiwan University
Taipei, 106 Taiwan
2Department of Computer Science and Information Engineering
National Chi Nan University
Nantou, 545 Taiwan
3Graduate Institute of Communication Engineering
National Taipei University
Taipei, 237 Taiwan

International Data Encryption Algorithm (IDEA) is one of the most popular cryptography algorithms in date since the characteristic of IDEA is suitable for hardware implementation. This study presents an efficient hardware structure for the modulo (2n + 1) multiplier, which is the most time and space consuming operation in IDEA. The proposed modulo multiplier saves more time and area cost than previous designs. With 16-bit input length, the proposed structure is 9.1% faster than that proposed by Zimmermann in 1999, and reduces the area about 35.22%. The proposed design enables IDEA to be implemented on hardware with high performance and low cost. Simulation results obtained from CPLD system developed by Altera indicate that the new design has 66Mb/sec encryption/decryption rate under 8.25MHz system clock rate with four pipeline stages for each round.

Keywords: Modulo (2n +1) multiplier, logic design, IDEA, security, cryptography

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Received May 31, 2005; revised September 16 & December 30, 2005; accepted February 22, 2006.
Communicated by Liang-Gee Chen.
*This paper was partially supported by the National Science Council under grant NSC 90-2219-E-260-001-, Taiwan, R.O.C.