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Journal of Information Science and Engineering, Vol. 28 No. 6, pp. 1091-1104 (November 2012)

A Bad-Block Test Design for Multiple Flash-Memory Chips

Department of Electronic Engineering
National Taiwan University of Science and Technology
Taipei, 106 Taiwan

Flash-memory has become a popular alternative in storage systems, due to its characteristics in non-volatility, shock-resistance, and low-power consumption. When a flash-memory chip is created priori to shipping, its initial bad blocks should be identified, where a bad block means that data stored in the block could be unreliable and can not be used. For safety and reliable reasons, any bad blocks should be efficiently identified by considering the operational model of flash-memory chips. In this paper, we will propose a bad-block test design for multiple flash-memory chips to efficiently identify bad blocks. The objective is to exploit execution parallelism and provide QoS guarantees. We will define a real-time task model and provide the schedulability analysis. We further provide a reasonable execution time setup for real-time tasks and show that the execution time setup can provide a schedulable result. In the experiments, a real case is discussed and measured such that the bad-block test design can be realized by configuring the corresponding computation time, the period, and the longest non-preemption time.

Keywords: design for testability, embedded systems, hardware/software co-design, flash memory

Full Text () Retrieve PDF document (201211_07.pdf)

Received December 20, 2010; revised September 1, 2011; accepted November 11, 2011.
Communicated by Tyng-Luh Liu.